When AI chip shortages come up, TSMC’s CoWoS packaging is one bottleneck that gets named. HBM is the other. The news often says “another memory maker’s HBM is sold out.” But what is HBM, and why do high-end AI GPUs so often use it?
This is the deep-dive version of Gate 2 in The AI Hardware Supply Chain, End to End, explained in plain words.
What Is HBM? One Sentence and One Picture
HBM stands for High Bandwidth Memory. It takes several layers of DRAM dies and stacks them vertically. It links them top to bottom with through-silicon vias (TSVs, vertical channels drilled through the chip). Then it sits right next to the GPU through a very wide interface.
The memory in an ordinary computer lies flat, one stick at a time on the motherboard. HBM stands the memory up and stacks it layer on layer, then moves it almost flush against the GPU. In one sentence: HBM is “ultra-wide memory that stands up,” built so the GPU never waits for data.
Stack it taller, make it wider, move it closer, and bandwidth can reach several terabytes per second. The cost: it needs advanced packaging such as CoWoS (the technology that puts the GPU and HBM in one package) to bond with the GPU. That makes it hard and expensive to make.
How It Differs From Ordinary Memory (DDR)
HBM will not replace the memory in your computer. The two serve different jobs.
DDR is general-purpose system memory: cheap and easy to expand, like a network of ordinary roads. HBM is a specialty part built for AI and high-performance computing: expensive, hard to make, and limited in production capacity. It is like an ultra-wide highway right next to the GPU, with a huge number of lanes and a very short trip. So a “memory shortage” and an “HBM shortage” are not the same thing.
Why HBM Suits High-End AI Chips
Think of the GPU as a powerful engine. Memory bandwidth is its fuel line. During AI training and inference, model weights and intermediate results keep moving into the compute cores. If data can’t arrive fast enough, thousands of cores sit idle and compute power is wasted.
That’s why flagship AI chips carry a lot of HBM. Take Nvidia’s Vera Rubin: the official spec is 288GB of HBM4 per GPU, with 19.2 TB per second of bandwidth.
The Three-Way Oligopoly
HBM is a three-player race with a very high barrier. New players can barely get in. Counterpoint estimates Q2 2026 HBM revenue shares at SK Hynix 50%, Samsung 33%, and Micron 18%.
SK Hynix has long led. In 2025 it was the first to announce it had finished developing HBM4, and it started volume shipments in Q2 2026. Samsung fell behind in the HBM3 generation. In February 2026 it was first to ship HBM4, and its revenue share rose from 21% in Q1 to 33% in Q2. Micron is third, and its HBM4 output is ramping up.
In June 2026, Jensen Huang said all three makers’ HBM4 had passed Vera Rubin qualification (according to Korean media). The next contest is over yield, supply volume, and how orders get split.
How HBM3e and HBM4 Differ, and What Comes Next
Each generation competes mainly on three things: how wide the interface is, how tall the stack can go, and how fast it runs.
| Generation | Interface | Bandwidth per stack | Status (as of October 2026) |
|---|---|---|---|
| HBM3e | 1024-bit | Over 1.2 TB/s | Most of HBM revenue in Q2 2026 (Counterpoint) |
| HBM4 | 2048-bit | Standard: up to 2 TB/s; Micron and Samsung products: about 2.8–3.3 TB/s | All three in mass production in 2026; used in Vera Rubin |
| HBM4E | Samsung and SK Hynix have sent samples; SK Hynix targets mass production in 2027 |
HBM4 doubles the interface width, like doubling the highway’s lanes again. The changeover is underway. Samsung expects HBM4 to be more than 60% of its HBM revenue in the second half of 2026. TrendForce expects HBM4E to ramp in the second half of 2027.
Another path is custom HBM. Nvidia unveiled its custom NVHBM in August 2026, and Micron says it is working with Nvidia on “the industry’s first custom HBM4E.” For more on HBM4, read What Is HBM4.
Why Supply Stays So Tight
HBM is complex to make, yields are hard to raise, and it must be paired with CoWoS advanced packaging. So capacity naturally grows slower than AI demand.
The result: long-term contracts lock up supply. In September 2026, Micron said it had already signed agreements with customers for the vast majority of its 2027 HBM supply, with prices up significantly year on year. It also expects the DRAM industry to stay tight in both 2027 and 2028. TrendForce likewise expects HBM demand to exceed supply in 2027. For the whole supply chain, even if GPU and packaging capacity grows, full systems still can’t ship if HBM can’t keep up.
Taiwan’s Role at This Gate
Taiwan has no HBM brand that it mass-produces at home. HBM is in the hands of South Korea’s SK Hynix and Samsung and America’s Micron. Micron has DRAM manufacturing sites in Taiwan, but the brand and product responsibility belong to Micron.
Downstream, the picture changes. HBM needs advanced packaging such as CoWoS to sit next to the GPU, and that step is highly concentrated in Taiwan. Many of the finished server racks are also assembled by Taiwanese firms. For example, Foxconn begins mass production of Vera Rubin racks from Q3 2026. So Taiwan’s role is in packaging, testing, and server assembly, and it moves directly with demand for AI accelerators.
Penchan’s summary
HBM, along with advanced packaging, is one of the parts that most often holds up the AI supply chain. Without enough bandwidth, even the strongest GPU can’t get its data.
When you read HBM news, watch three things: how the three makers’ rankings change, how far the move from HBM4 to HBM4E and custom HBM has gone, and how long tight supply will last.
To see how HBM is tied to the GPU, read What Is CoWoS. To see how the whole chain fits together, go back to the supply-chain overview.